1. Field of the Invention
The present invention relates generally to a bias voltage generating circuit applicable to a semiconductor memory such as an EPROM (Erasable Programmable Read Only Memory), and more particularly to a bias voltage generating circuit for supplying a bias voltage to bit lines.
2. Description of the Related Art
FIG. 1 shows a read-out circuit of a general EPROM. One end of a sense line 11 and one end of a reference line 12 are connected to a differential amplifier 13 which constitutes a sense amplifier. The sense line 11 is connected to one end of a current path of each of a plurality of bit line selection transistors Q2, which constitute a Y selector 14, via a transistor Q2 functioning as a transfer gate. The other ends of the current paths of these transistors Q2 are connected to bit lines BL. The bit lines BL are connected to memory cells Q3 which store the data. Thus, a memory cell array 15 is constructed.
The other end of the reference line 12 is connected to a reference cell Q6 for reference, via a transistor Q4 functioning as a transfer gate and a transistor Q5 constituting a reference selector. The reference cell Q6 is always in the erase state.
The sense lines 11 and 12 are connected to a power supply Vcc via transistors Q7 and Q8 functioning as leads. The gates of the transistors Q1 and Q4 are connected to an output node of a bias voltage generating circuit 16 for generating a bias voltage Vbias.
In the above structure, the differential amplifier 13 compares the level of the sense line 11, which varies in accordance with the data stored in the selected memory cell Q3, and the level of the reference line 12 which is constant, thereby determining the data stored in the memory cell Q3.
The operation for reading out data "1" from the memory cell Q3 will now be described. The memory cell Q3 which stores data "1" is an erase-state cell having a low threshold voltage. Accordingly, this transistor is rendered conductive when it is selected. In this case, the charge of the sense line 11, which is charged by the transistor Q7, is discharged via the transistors Q1 and Q2, bit line BL and memory cell Q3. Accordingly, the bit line BL is set at a low voltage, e.g. about 1.0 V, at which the charge current of the transistor Q7 is balanced with the discharge current of the memory cell Q3.
The operation for reading out data "0" from the memory cell Q3 will now be described. The memory cell Q3 which stores data "0" has a high threshold voltage. Accordingly, even when this transistor is selected, it is not rendered conductive. Even if it is rendered conductive, a flowing current is much lower than in the case of the cell storing data "1." Accordingly, the sense line 11 and bit line BL are charged by the transistor Q7 and the potential thereof rises. However, suppose the case where the bias voltage output from the bias voltage generating circuit is Vbias and the threshold of the transistor Q1, which is determined in consideration of the back gate bias, is Vthn. In this case, when the potential of the bit line BL becomes Vbias-Vthn or above, the transistor Q1 is turned off and the bit line BL is no longer charged.
On the other hand, when the threshold of the transistor Q7 is Vthp, the potential of the sense line 11 is raised to Vcc-Vthp. In addition, the potential of the bit line BL at the time of read-out is clamped to Vbias-Vthn by the bias voltage. The potential of the reference line 12 is determined similarly with that of the sense line 11 by using the reference cell Q6. However, by making the size of the transistor Q8 larger than that of the transistor Q7 and increasing the charge potential, the potential of the reference line 12 is approximately set at the intermediate potential value of the swing of the sense line 11 due to the variation of data "1" and "0".
The bit line potential at the read-out time is clamped to Vbias-Vthn for the following reason: As is well known, when data is written in a memory cell, the control gate and drain are set at a high potential for writing, e.g. much higher than Vcc, and hot electrons are injected in the floating gate.
However, even in the case where the potential of the control gate and drain is low, if a stress is applied for a long time, a slight quantity of electrons are injected in the floating gate, that is so-called soft write. Thus, the bit line potential at the readout time must be set, with the variation of data due to soft write taken into account.
Specifically, it is necessary that the variation in threshold due to soft write does not affect normal operation, even if the data "1" in the memory cell is read out many times during the term of guarantee of, e.g. 10 years. Thus, the bit line potential is clamped at a low level by using the bias voltage. For example, the bit line voltage is normally set at about 1.0 V. L When data "0" is read out from the memory cell, the upper level of the bit line potential is clamped. Thus, the level difference between the upper limit and the bit line potential at the time of reading out data "1" from the memory cell can be clamped to, e.g. about 0.2 to 0.3 V. The bit line is provided with inherent drain diffusion capacitances of a number of memory cells. However, since the level difference between data "1" and data "0" is small, the time required for a variation in level is short and high speed access is achieved.
Since the potential of the sense line 11 separated from the bit line by the transistor Q1 functioning as a transfer gate swings in a wide range, as stated above, the margin of the differential amplifier 13 can be increased.
The bias voltage generating circuit 16 will now be described. The bit line potential is clamped to Vbias-Vthn, as described above. Thus, when the level of the bias voltage Vbias varies due to noise, etc., the level of the bit line varies accordingly. Once the level has varied, however, it takes a long time until the varied level restores to the original level since the bit line has a large inherent capacitance. Thus, the differential amplifier 13 requires a long time for determining the data. It is therefore important that the bias voltage Vbias is not affected by power supply noise.
Further, when the write amount is checked, etc., the level of the power supply voltage Vcc is raised to more than normal level. In this case, in order to prevent the soft write, it is desirable that the bias voltage Vbias be constant without being influenced by the power supply voltage Vcc.
FIG. 2 shows a conventional bias voltage generating circuit.
The gate and source of a depletion type N-channel transistor N1 are connected to an output node 16a. This transistor functions as a load, and its drain is connected to the drain of a P-channel transistor P1. In the standby mode, the transistor P1 cuts off a current flowing to the transistor N1. It has a sufficient size so that the current is limited by only N1. The source of the transistor P1 is connected to a first power supply Vcc, and the gate thereof is supplied with a chip enable signal/CE.
The gate and drain of an enhancement type N-channel transistor N2 are connected to the output node 16a. The source of the transistor N2 is connected to the gate and drain of an enhancement type N-channel transistor N3. The source of the transistor N3 is connected to a second power supply, e.g. a ground potential. The output node 16a is connected to a drain of the enhancement type N-channel transistor N4. The source of the transistor N4 is connected to the second power supply, and the gate thereof is supplied with a chip enable signal/CE. The transistor N4 resets the bias voltage Vbias output to a ground level.
In the above structure, when the chip enable signal/CE lowers to a low level, the transistor P1 is rendered conductive and a current flows to the transistors N1, N2 and N3.
FIG. 3 shows current characteristics (load characteristics) of the circuit shown in FIG. 2. In FIG. 3, I1 indicates a current flowing through the transistor N1, and I23 a current flowing through the transistors N2 and N3. As is shown in FIG. 3, the current I23 starts to flow when the bias voltage Vbias rises to about 2 Vthn or more. To be accurate, the threshold of the transistor N2 is slightly increased by a back bias effect. An intersection A between the current I23 and current I1 denotes the bias voltage Vbias which corresponds to the threshold 2 Vthn+.alpha.. In the vicinity of intersection A, the transistor N1 operates in a saturated region. Thus, even when the power supply voltage Vcc varies and I1 varies, as indicated by a dash-and-dot line, as shown in FIG. 3, the position of intersection A hardly changes. Accordingly, the bias voltage Vbias is substantially constant, independently of the potential of the power supply Vcc.
The bias voltage generating circuit 16 is constituted by an analog circuit. By contrast, it is common that recently developed devices such as EPROMs are constituted by CMOS circuits and power consumption is reduced. Accordingly, it is desirable that a DC flowing through the bias voltage generating circuit be low. For this purpose, it is necessary that the size of the depletion type N-channel transistor N1 be reduced and the current be decreased. However, at the standby time, the transistor P1 cuts off DC and the transistor N4 sets the bias voltage Vbias to a ground potential. Thus, the rising time of the bias voltage when the chip is selected and activated is delayed by decreasing the size of the transistor N1. Therefore, the size of the transistor N1 cannot be reduced unnecessarily.
With the miniaturization of the feature size of the memory cell such as gate length, insulating film thickness, etc., the memory cell becomes more sensitive to the write operation. Thus, in order to prevent soft write, it is necessary to further reduce the bit line potential in the read mode. Specifically, in the case of the circuit shown in FIG. 2, it is necessary to reduce the potential c shown in FIG. 3. In this case, however, a problem arises if the size of the transistor N1 is reduced excessively.
On the other hand, FIG. 4 shows the relationship between the bias voltage Vbias and bit line potential Vbit in the circuit shown in FIG. 2. As has been described above, the bias voltage Vbias is constant in the range of power supply voltage Vcc in which the circuit operates normally. However, in the range in which the bias voltage Bias is constant, the bit line potential Vbit lowers as the power supply voltage Vcc rises. In other words, since the power supply voltage Vcc is applied to the gate of the memory cell, the current flowing through the memory cell increases when the power supply voltage rises.
In FIG. 4, the bit line potential takes a maximum value at point PA, above where the bias voltage Vbias does not depend on the power supply voltage Vcc. Thus, at point PA the bias voltage Vbias is lower than a normal operation voltage Vcc=5 V. Accordingly, if the upper limit of the bit line potential, determined in consideration of soft write, is Vsoft, the bit line potential Vbit at point PA is limited to Vsoft. Then, in actual operation point PB, the bit line potential Vbit is lower than the potential Vsoft. Accordingly, the current flowing through the memory cell at operation point PB decreases by a degree corresponding to the lowering of the drain voltage, and the access time becomes worse than in the case of the potential Vsoft.